1. Field of the Invention
The present invention relates to a semiconductor device (e.g., a static random access memory (SRAM) device) including back-gated transistors, and more particularly, to a device which includes a back-gate transistor which may be fabricated using finFET technologies (e.g., a coupled backgate finFET SRAM).
2. Description of the Related Art
FIG. 1 provides a circuit diagram illustrating a conventional six transistor (6-T) SRAM device 100. As illustrated in FIG. 1, the conventional SRAM device 100 includes n-type field effect transistors (nFETs) N1-N4, and p-type field effect transistors (pFETs) P1-P2. The word line (wl) is coupled to the gates of nFETs N3, N4 and the bit lines blt, blc are coupled to an arm of nFETs N3, N4, respectively.
In advanced semiconductor devices (e.g., such as the conventional SRAM device 100), dopant fluctuations are becoming a serious problem in Vt (threshold voltage) control. As semiconductor devices become smaller and smaller, Vt control becomes more difficult. This problem greatly affects SRAM devices since the SRAM devices may be very small.
A known solution to this problem is to control the Vt by using back-gates in the semiconductor devices. One serious problem with this solution, however, is that the use of back-gates in semiconductor devices results in increased layout complexity, and therefore, higher cost. In addition, separately back gating the individual devices increases wiring densities and does not help in the layout compactness.